Semiconductor devices are essential elements for producing electronic products. Updates of the semiconductor devices have been a driving force for the development of semiconductor technologies and the progress of the semiconductor industry, especially for the elevation of the performance of Central Processing Units (CPU) and memories. Since the end of the last century, the process for manufacturing chips have been developed very rapidly, the level of which has been evolved from micrometers to a technology under 32 nm now.
Under a circumstance that photolithography technologies have a limitation to be improved further and advanced photolithography technologies are impossible to be used to obtain a mass production, the implementation of continually reducing patterns to a minimum would imply a constant increase of the cost and a decrease of the yield. At present, taking an example of a 45 nm planar transistor process, which has reached to the process limitation, a serious short-channel effect is introduced, thus causing a raise of an off-state current and a lowering of a transconductance, etc. Improving the gate control capability of a semiconductor device has become a current research focus, where a surrounding-gate device is one of the important devices for obtaining excellent gate control capability and alleviating the short-channel effect.
Meanwhile, when a new manufacturing process is to be put into use, tests for the reliability of the gate dielectric of a semiconductor device manufactured by such process is also a very important subject. Since electron traps and hole traps in the gate dielectric layer of the semiconductor device, i.e. certain dangling bonds or defects, would cause a drift of a threshold voltage of the device and a decrease of an on-state current, thus resulting in a serious negative/positive bias temperature instability (NBTI/PBTI), and at the same time would cause an increase of a gate-drain current to shrink the reliability and the life of the device. Researches and tests for the traps in the dielectric layer may provide an optimal solution for manufacturing the device, and tests of the reliability for traps is in turn an important way for characterizing the life span.
A relatively precise method for testing traps for conventional planar transistor devices is a charge pump test, in which the device is required to have substrate contact for signals. However, in novel devices such as a surrounding-gate device, contacts only exist at three terminals, i.e. the gate, the source and the drain terminal, therefore, it is impossible to apply the typical charge pump test to the semiconductor device having no substrate contact. At present, for the surrounding-gate device, a test for traps in its three-dimensional surrounded type gate dielectric has become a focus question in manufacturing integrated circuits.